A latch with clock enable is a standard logic circuit used in the design of various digital logic systems including, but not limited to, computer systems. A latch is a data storage element used to hold a given logic state when a CLOCK input to the latch is switched to an appropriate state, commonly referred to as a latch mode. When the CLOCK input is switched to an opposite state, the latch operates to transmit a logic value at its data input directly to its output. This is commonly referred to as a transparent mode.
Emitter coupled logic is a known circuit design method using bipolar junction transistors coupled together to form a differential amplifier. Generally, the emitters of parallel transistors are coupled to one another and the transistors are biased so that the transistor having sufficiently more positive voltage applied to its base will draw .all of the current flow through the differential amplifier circuit and hence, function as a current switch. Multiple differential amplifiers can be arranged in various logic levels to provide logic functions, as for example, a latch.
In an ECL latch, an upper logic level includes differential amplifiers arranged to provide a data capture circuit and a data latch output circuit. In addition, a lower logic level is coupled to the upper logic level and includes a differential amplifier having differential clock inputs to gate current through either the data capture circuit, during the transparent mode, or the data latch output circuit, during the latch mode, as a function of a CLOCK input signal.
Typically, the CLOCK input signal is transmitted as differential clock signals by a system clock source. The differential clock signals are distributed by the system clock source to the lower logic level of each of a plurality of latches arranged throughout a computer system. The system clock changes in a predetermined frequency from a first state to a second state, causing all of the latches coupled to the system clock source to alternate between the latch mode and the transparent mode.
In certain computer system designs, a clock enable circuit is coupled to each latch circuit so that preselected individual latches in the system can be controlled to continue to hold data irrespective of state changes in the system clock source, while other latches in the system continue to alternate between the latch and transparent modes under the control of the system clock source. The clock enable circuit of each latch includes an enable input arranged to control the enable circuit through the use of appropriate logic state signals that can be asserted at the enable input. Thus, logic signals can be used to either enable clock control or inhibit clock control of latch operation, as desired.
Each of the first and second states of the clock signal comprises a clock pulse of a predetermined time period. When the clock changes state from the first state to the second state and then back to the first state, the latch circuit would have to transition from the latch mode to the transparent mode, so that data at the input of the latch can be accepted by the latch, and then back to the latch mode to hold the data. The transition through the modes would have to occur within the time period of the clock pulse of the second clock state. Thus, as the speed of operation of the computer system increases, the time period available during the transparent mode, as determined by the second clock pulse, for each latch circuit to transition through the transparent mode to accept data, decreases. This is particularly true when the pulse of the second state of the clock is of shorter duration than the pulse of the first state of the clock, e.g. in the order of 250 pico seconds.
The speed of operation of a latch circuit is generally determined by the switching speeds of the transistors used in the latch circuit and the amount of electrical current used to drive the transistors. High currents help to discharge internal circuit capacitances such that the circuit generally operates at faster speeds. The switching speed of a transistor is a characteristic of the device and once a circuit designer selects the fastest transistor available for a particular implementation, the amount of current used to drive the transistors is the factor available for change, so as to further increase the speed of operation of the latch circuit. However, there must be a proper balancing between the power dissipation within a circuit caused by the use of high currents and the speed of operation of the circuit. Any trade-off between speed and power dissipation is ultimately limited by the delay-power characteristic of the process technology used to fabricate the latch circuit. The intrinsic delay-power characteristic is determined largely by the physical and electrical attributes of active and passive components that can be manufactured by a given process.